The invention relates to an integrated memory circuit which is divided into a number of memory blocks, each of which comprises memory cells which are arranged in rows and columns, the memory cells which are arranged in a column being connected to a column selection line while in several memory blocks the memory cells which are arranged in a row are connected to a row selection line, a row of memory cells in a memory block being activatable via a logic row selection gate whereto a row selection signal RS and a block selection signal BS are applied.
A memory circuit of this kind is known from ISSCC, Digest of Technical Papers, February 1983, pages 58-59. In this circuit the block selection signal BS and the row selection signal RS are applied to an AND-gate for the selection of a row of memory cells in a memory block. In practice an AND-gate consists of an inverting AND-gate whose output is connected to an inverting amplifier so that the circuit is large (6 transistors) and slow (due to 2 gate delays). A further possibility consists in the selection of a row in a memory block by means of an inverting OR-gate which should in that case receive the inverted block selection and row selection signals BS and RS. When CMOS transistors are used, however, this solution again results in a large and slow block selection circuit, because the PMOS transistors must be very wide in order to achieve the same power supply capacity (as the AND-gate), so that the input capacitances are high. The switching of the OR-gate is fast, but more time is required for charging these input capacitances. For example, in a 256 k memory the block selection signal BS has to drive 256 (or 512, 1024, depending on the memory organization) row selection gates in parallel.